The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like field effect transistor (FinFET) device. A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.
However, conventional FinFET devices may still have certain drawbacks. One drawback is that, for FinFET devices that are used for electrostatic discharge (ESD) protection, the drain region is substantially wider than the source region (and wider than drain regions of other non-ESD type of FinFET devices. The longer drain site may lead to poor epitaxial growth, which may cause metal contact landing problems. For example, the metal contact that is supposed to be formed on the ESD drain site may actually have connection problems with the ESD drain site. The poor connection between the ESD drain site and the metal contact consequently degrades device performance and may even lead to device failures.
Therefore, while existing FinFET devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.